1. Field of the Invention
The present invention relates to a current source with immunity for the variation of threshold voltage, and more particularly, to a current source for lowering the impact of the threshold voltage on the magnitude of the current, by increasing the voltage difference between the gate and the source of the current source.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional current mirror. As shown in FIG. 1, the gate (control end) of the P-type Metal Oxide Semiconductor (PMOS) transistor QP1 is utilized to receive a control voltage VG, the source (first end) of the PMOS transistor QP1 is coupled to a voltage source VDD, and the drain (second end) of the PMOS transistor QP1 is utilized to output a current I1. The gate (control end) of the PMOS transistor QP2 is utilized to receive the control voltage VG, the source (first end) of the PMOS transistor QP2 is coupled to the voltage source VDD, and the drain (second end) of the PMOS transistor QP2 is utilized to output a current I2. The conventional current mirror utilizes the control voltage VG to bias the PMOS transistor QP1 for generating the reference current source I1, and then the ratio of the channel aspect ratios (width/length, W/L) of the PMOS transistors QP1 and QP2 is utilized to generate the current I2, which is proportional to the reference current source I1. For instance, if the channel aspect ratio (W1/L1) of the PMOS transistor QP1 is “1” and the channel aspect ratio (W2/L2) of the PMOS transistor QP2 is “2”, then when the reference current source I1 is 1 amp, the current I2 is generated to be 2 amps.
The conventional current mirror operates the PMOS transistor QP1 in the saturation region. In other words, the relationship between the current I1 and the voltage VG is described in the formulas as below:I1=½×K×(W1/L1)×(VSG−VT)2  (1);=½×K×(W1/L1)×(VDD−VG−VT)2  (2);where the voltage VSG represents the voltage difference, which is equivalent to the voltage of (VDD−VG), between the source and the gate of the PMOS transistor QP1, the voltage VT represents the threshold voltage of the PMOS transistor QP1, and K represents a process variable. Hence, the magnitude of the reference current source I1 is related to the channel aspect ratio (W1/L1) of the PMOS transistor QP1, the voltage difference VSG (equivalent to (VDD−VG)), and the threshold voltage VT.
Due to the magnitude of the threshold voltage VT is easily affected by the processing, when under different processing, the magnitude of the current source I1 is still affected by the threshold voltage VT, even with the same voltage source VDD, the same voltage difference VSG between the source and the gate, and the same channel aspect ratio (W/L). In this way, the magnitude of the current source differs from the desired.